Semiconductor device and manufacturing method thereof

ABSTRACT

A method for efficiently manufacturing a semiconductor device, the semiconductor device having an FET and a pn junction diode provided on the same semiconductor substrate, the FET having a Schottky junction for a gate electrode and a gate recess, includes the steps of forming a channel layer, a first etching stopper layer, an n-type common layer, a second etching stopper layer, a p-type layer, and a third etching stopper layer on the semiconductor substrate in that order; etching away the p-type layer and the third etching stopper layer in specific regions; simultaneously forming a source electrode, a drain electrode, a cathode; forming a mask having an opening for forming a gate recess and a gate electrode and an opening for forming an anode; forming the gate recess by etching while the third etching stopper layer prevents the p-type layer from being etched; and simultaneously forming the gate electrode and the anode.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to semiconductor devices andmanufacturing methods thereof, and more particularly, relates to asemiconductor device including a field effect transistor and a diode onthe same semiconductor substrate, and also relates to a manufacturingmethod thereof.

[0003] 2. Description of the Related Art

[0004] As a technique for forming a field effect transistor (FET) and adiode on the same semiconductor substrate, for example, techniquesdisclosed in Japanese Unexamined Patent Application Publication Nos.8-340213 and 8-255838 may be considered.

[0005] In Japanese Unexamined Patent Application Publication No.8-340213, a technique has been disclosed in which, on the samesemiconductor substrate, a part of one layer is used an active layer fora Schottky diode, and another part of the one layer is used as an activelayer for an FET.

[0006] In addition, in Japanese Unexamined Patent ApplicationPublication No. 8-255838, the structure has been disclosed in which aPIN diode, an FET, and a heterojunction bipolar transistor (HBT) areformed on the same semiconductor substrate. In this structure, for thePIN diode, the FET, and the HBT, the individual active layers are formedseparately.

[0007] According to Japanese Unexamined Patent Application PublicationNo. 8-340213, a contact layer of an anode of a Schottky diode andcontact layers of a drain and a source electrode of an FET are formedfrom the same layer. However, when the contact layers mentioned aboveare only formed from the same layer, only one step of forming a layercan be omitted in a process for growing active layers. As a result, theeffect of reducing the number of manufacturing steps and the effect ofreducing cost cannot be fully achieved. In addition, according toJapanese Unexamined Patent Application Publication No. 8-340213,although a manufacturing method of a semiconductor device disclosedtherein has not been clearly described, due to variations in degree ofetching in an etching step which may be necessary for the manufacturing,variations in properties of the diode and the FET may be increased insome cases.

[0008] On the other hand, according to the technique disclosed inJapanese Unexamined Patent Application Publication No. 8-255838, sincethe active layers of the diode, the FET, and the HBT are individuallyformed by selective growth, reduction in number of manufacturing stepsand reduction in cost cannot be sufficiently achieved.

[0009] In addition to the desire of forming the active layer of an FETand that of a diode from a common layer, in order to reduce the numberof manufacturing steps, it has been desired that at least one electrode(a gate electrode, a drain electrode, or a source electrode) of the FETand at least one electrode (an anode and a cathode) of the diode arepreferably formed at the same time.

[0010] When an FET having a Schottky junction for a gate electrode and adiode having a Schottky junction are formed on the same semiconductorsubstrate, since a layer is provided which is used in common for theactive layers thereof, the desire described above can be relativelyeasily fulfilled.

[0011] On the other hand, when an FET, which has a Schottky junction fora gate electrode and has a gate recess, and a pn junction diode areformed on the same semiconductor substrate, the desire described abovecannot be so easily fulfilled for the following reasons.

[0012] That is, when a drain electrode and a source electrode of the FETare formed on respective contact layers, and a cathode of a diode issimultaneously formed on an n-type layer which is the same type as thatof the contact layers, since these electrodes are ohmic electrodes to ann-type layer, by using the same metal, the formation of the electrodesdescribed above can be easily realized. However, metals for a gateelectrode, which is a Schottky electrode, and an anode of a diode, whichis an ohmic electrode provided on a p-type layer, are formed of adifferent type of metal from that for the drain electrode and the like,and hence the electrodes described above must be formed in a separatestep.

[0013] It is not always impossible to simultaneously form a gateelectrode, a drain electrode, and a source electrode. However, since aspecific step must be additionally required, it is not practical inorder to achieve cost reduction. In addition, although both the anodeand the cathode are ohmic electrodes in view of functionality, the typesof semiconductor layers on which they are to be formed are differentfrom each other, that is, a p-type layer and an n-type layer, differentelectrode materials must be used, and as a result, the anode and thecathode cannot be simultaneously formed.

[0014] According to the situations described above, a desire may arisein that at least a gate electrode and an anode are simultaneouslyformed. When the gate electrode is formed, a mask is formed for forminga gate recess, and recess etching is then performed. Subsequently, ingeneral, by using the same mask as described above without being removedfrom the position for the recess forming, a step of forming a gateelectrode is performed by deposition or the like.

[0015] As described above, the reason that the same mask is used in theetching step of forming the gate recess and in the step of forming thegate electrode by deposition or the like is that by using the same mask,the gate electrode can be formed while the positional accuracy obtainedin forming the gate recess is maintained. When a different mask is used,or when once the mask is removed and is then again disposed, the gateelectrode cannot be formed with high positional accuracy.

[0016] As described above, when the gate electrode and the anode aresimultaneously formed using the same mask as that used for forming thegate recess, it is necessary that the mask has an opening at a positionat which the anode is to be formed, that is, at which a p-type layer isto be exposed. However, when an opening is provided in the mask forexposing the p-type layer, in an etching step of forming the gaterecess, the p-type layer is also etched, and as a result, itdisadvantageously becomes difficult to form a diode having desiredproperties.

SUMMARY OF THE INVENTION

[0017] In order to overcome the problems described above, preferredembodiments of the present invention provide a manufacturing method of asemiconductor device, which can solve the problems described above, andis also to provide a semiconductor device which is advantageously formedby the manufacturing method described above.

[0018] According to a preferred embodiment of the present invention, asemiconductor device includes a semiconductor substrate, a field effecttransistor provided thereon, the transistor having a gate recess and aSchottky junction for a gate electrode, and a pn junction diode providedon the semiconductor substrate, the diode having an n-type layer and ap-type layer, wherein at least one of electrodes of the field effecttransistor and at least one of electrodes of the diode are composed ofmetal conductors which are simultaneously formed.

[0019] In the semiconductor device described above, a source electrodeand a drain electrode of the field effect transistor and a cathode ofthe diode are preferably composed of metal conductors which aresimultaneously formed, and in addition, the gate electrode of the fieldeffect transistor and an anode of the diode are preferably composed ofmetal conductors which are simultaneously formed.

[0020] In addition, at least one of active layers of the field effecttransistor and at least one of active layers of the diode are preferablycomposed of layers which are obtained from a common active layerprovided on the semiconductor substrate by epitaxial growth. In the casedescribed above, contact layers of the field effect transistor and then-type layer of the diode are preferably composed of layers which areobtained from a common n-type layer provided on the semiconductorsubstrate by epitaxial growth. Furthermore, it is more preferable thatthe contact layers are provided on a channel layer on the semiconductorsubstrate of the field effect transistor and that the p-type layer ofthe diode is provided on the n-type layer thereof.

[0021] As described above, when at least one of the active layers of thefield effect transistor and at least one of the active layers of thediode are obtained from the common active layer, the active layer of thefield effect transistor is preferably separated from the active layer ofthe diode by ion implantation or etching.

[0022] According to another preferred embodiment of the presentinvention, a method for advantageously manufacturing a semiconductordevice which includes a semiconductor substrate, a field effecttransistor provided thereon, having a gate recess and a Schottkyjunction for a gate electrode, a pn junction diode provided on thesemiconductor substrate, and the structure as described above, is suchthat a step of preparing the semiconductor substrate is first performed,and subsequently, a channel layer for the field effect transistor, afirst etching stopper layer, an n-type common layer used for contactlayers for the field effect transistor and for an n-type layer for thediode, a second etching stopper layer, a p-type layer for the diode, anda third etching stopper layer are formed on the semiconductor substratein that order by epitaxial growth.

[0023] Next, an etching step is performed which etches away the p-typelayer and the third etching stopper layer in regions in which the fieldeffect transistor and a cathode of the diode are to be formed while theetching is to be stopped by the second etching stopper layer. That is,etching is performed so that a region remains in which the p-type layerof the diode is to be formed.

[0024] Subsequently, a step is performed which simultaneously forms asource electrode and a drain electrode for the field effect transistorand the cathode for the diode so as to have an ohmic contact with then-type common layer.

[0025] Next, a step is performed which forms a mask having openingswhich expose a region of the n-type common layer in which the gaterecess for the field effect transistor is to be formed and at least aportion of the third etching stopper layer.

[0026] While the third etching stopper layer prevents the p-type layerfrom being etched, a step of performing etching through the mask forforming the gate recess in the n-type common layer is performed so thatthe etching is to be stopped by the first etching stopper layer.

[0027] Next, a step is performed through the same mask as describedabove which simultaneously forms the gate electrode for the field effecttransistor which has a Schottky contact with the channel layer and ananode for the diode which has an ohmic contact with the p-type layer,and subsequently, the mask is removed.

[0028] The method for manufacturing a semiconductor device, according tovarious preferred embodiments of the present invention, may furtherinclude, after the etching step described above: a step of performingetching or ion implantation for the channel layer and the n-type commonlayer in order to separate a region in which the field effect transistoris to be formed from a region in which the diode is to be formed.

[0029] In addition, the third etching stopper layer is preferably formedto have a thickness that is preferably larger than the total thicknessof the first and the second etching stopper layers.

[0030] Other features, elements, steps, processes, characteristics andadvantages of the present invention will become more apparent form thefollowing detailed description of preferred embodiments with referenceto the attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0031]FIG. 1 is a schematic cross-sectional view of the structure formedin a first step of a manufacturing method of a semiconductor device,according to one preferred embodiment of the present invention;

[0032]FIG. 2 is a schematic cross-sectional view of the structure formedin a second step performed after the first step mentioned with referenceto FIG. 1;

[0033]FIG. 3 is a schematic cross-sectional view of the structure formedin a third step performed after the second step mentioned with referenceto FIG. 2;

[0034]FIG. 4 is a schematic cross-sectional view of the structure formedin a fourth step performed after the third step mentioned with referenceto FIG. 3;

[0035]FIG. 5 is a schematic cross-sectional view of the structure formedin a fifth step performed after the fourth step mentioned with referenceto FIG. 4;

[0036]FIG. 6 is a schematic cross-sectional view of the structure formedin a sixth step performed after the fifth step mentioned with referenceto FIG. 5;

[0037]FIG. 7 is a schematic cross-sectional view of the structure formedin a seventh step performed after the sixth step mentioned withreference to FIG. 6;

[0038]FIG. 8 is a schematic cross-sectional view of the structure of asemiconductor device formed in an eighth step performed after theseventh step mentioned with reference to FIG. 7;

[0039]FIG. 9 is a schematic cross-sectional view of the structure formedin a step corresponding to the step mentioned with reference to FIG. 3for illustrating a manufacturing method of a semiconductor device,according to another preferred embodiment of the present invention; and

[0040]FIG. 10 is a schematic cross-sectional view of the structure of asemiconductor device formed in a step corresponding to the stepmentioned with reference to FIG. 8, according to the preferredembodiment mentioned in FIG. 9.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0041] FIGS. 1 to 8 are schematic views for illustrating preferredembodiments of the present invention; a semiconductor device 1 is shownin FIG. 8 as a finished product; and typical steps performed for formingthe semiconductor device 1 are sequentially shown in FIGS. 1 to 7. InFIGS. 1 to 8, the steps of manufacturing one semiconductor device 1 areshown. However, a plurality of semiconductor devices 1 is actuallyformed on a semiconductor wafer having a relatively wide area. Inaddition, in the cross-sectional views shown in FIGS. 1 to 8, thedimension is exaggerated in the thickness direction to some extent, andin order to more clearly show the individual elements in the figures,the dimensions thereof are not always shown accurately.

[0042] With reference to FIG. 1, a semiconductor substrate 2 is firstprepared. For example, the semiconductor substrate 2 is preferablycomposed of GaAs.

[0043] Next, on the semiconductor substrate 2, using a method such asmolecular beam epitaxy (MBE) or metalorganic chemical vapor deposition(MOCVD), active layers for a field effect transistor (FET) and activelayers for a diode are formed by epitaxial growth as described below.

[0044] First, a channel layer 3 for the FET is formed. The channel layer3 is formed, for example, of an n-type GaAs.

[0045] Next, on the channel layer 3, a first etching stopper layer 4 isformed, and this etching stopper layer 4 is formed, for example, ofAlGaAs.

[0046] Subsequently, on the first etching stopper layer 4, an n-typecommon layer 5 is formed which is used as contact layers for the FET andan n-type layer for the diode. The n-type common layer 5 is formed, forexample, of n-type GaAs. The thickness of the n-type common layer 5 andthe concentration of an impurity contained therein are determined so asto sufficiently decrease the contact resistance. In general, thethickness of the n-type common layer 5 is, for example, about 10 nm toabout 100 nm, and the concentration of an n-type impurity is set to anoptional value in the range of from about 1×10¹⁸ to about 1×10¹⁹/cm³.

[0047] On the n-type common layer 5, a second etching stopper layer 6 isformed. This etching stopper layer 6 is also formed, for example, ofAlGaAs as is the first etching stopper layer 4.

[0048] Next, on this second etching stopper layer 6, a p-type layer 7 isformed for the diode. This p-type layer 7 is formed, for example, ofp-type GaAs. The thickness and the concentration of an impuritycontained in the p-type layer 7 are determined in accordance with thefunctions of the diode which is to be formed. For example, when a Zenerdiode is formed, the thickness is preferably in the range of from about10 nm to about 100 nm and the concentration of a p-type impurity is setin the range of from about 5×10¹⁷/cm³to about 1×10¹⁹/cm³. When avaractor diode is formed, the thickness is preferably in the range offrom about 10 nm to about 100 nm, and the concentration of a p-typeimpurity is preferably in the range of from about 1×10¹⁷/cm³to about1×10¹⁸/cm³ so as to be inclined in the depth direction.

[0049] On the p-type layer 7, a third etching stopper layer 8 is thenformed. As is the first and the second etching stopper layers 4 and 6,this etching stopper layer is also formed, for example, of AlGaAs.

[0050] The thicknesses of the first, the second, and the third etchingstopper layers 4, 6, and 8 are to be determined in accordance with theselectivity obtained in etching steps described later but are generallyin the range of from about 3 nm to about 20 nm. As can be seen from thestep described later, the third etching stopper layer 8 preferably has athickness that is larger than the total thickness of the first and thesecond etching stopper layers 4 and 6, and as one example, the thicknessof the third etching stopper layer 8 is approximately three times thethickness of each of the first and the second etching stopper layers 4and 6.

[0051] In addition, the second etching stopper layer 6 may be formed ofa p-type, an n-type, or an i-type semiconductor, and in accordance withthe type of semiconductor, a pn junction position of the diode ischanged. When the second etching stopper layer 6 is formed of a p-typesemiconductor, the interface between the second etching stopper layer 6and the n-type common layer 5 becomes a pn junction surface; when thesecond etching stopper layer 6 is formed of an n-type semiconductor, theinterface between the second etching stopper layer 6 and the p-typelayer 7 becomes a pn junction surface; and when the second etchingstopper layer 6 is formed of an i-type semiconductor, the centralportion of the second etching stopper layer 6 in the thickness directionbecomes a pn junction surface.

[0052] The carrier concentrations of the etching stopper layers 4, 6,and 8 are determined so that the functions of the FET and the diode arenot damaged.

[0053] Next, as shown in FIG. 2, a mask 9 is formed by aphotolithographic technique so as to cover a portion of the p-type layer7 at which the active layer of the diode is to be formed.

[0054] As also shown in FIG. 2, etching is performed through the mask 9,and by this etching, the p-type layer 7 and the third etching stopperlayer 8 in regions in which the FET is to be formed and a cathode of thediode is to be formed are removed. This etching is stopped by the secondetching stopper layer 6. By this etching step, a portion of the p-typelayer 7 is allowed to remain which is formed into a p-type layer of thediode.

[0055] This etching may be performed by dry etching or wet etching. Whenwet etching is performed, as an etching solution, for example, asolution containing phosphoric acid, hydrogen peroxide, and water, or asolution containing citric acid, hydrogen peroxide, and water may beadvantageously used, and when an etching solution is appropriatelyselected as described above, the etching can be easily stopped by thesecond etching stopper layer 6 made of AlGaAs.

[0056] In addition, although not shown in the figure, by this etching,alignment marks to be used in a subsequent photolithographic step arepreferably formed at the same time.

[0057] After the etching described above is completed, the mask 9 isremoved using an organic solvent and/or oxygen plasma.

[0058] Next, as shown in FIG. 3, in order to separate a region in whichthe FET is to be formed from a region in which the diode is to beformed, ion implantation is performed for the channel layer 3 and then-type common layer 5, thereby forming the ion implanted regions 10. Inthis preferred embodiment, the ion implanted regions 10 are formed so asto reach the semiconductor substrate 2.

[0059] In more particular, a mask 11 is formed using a photolithographictechnique so as to cover regions in which the active layers of the FETand the diode are to be formed, and ion implantation is performedthrough the mask 11 for regions other than the regions in which theactive layers of the FET and the diode are to be formed, thereby formingthe ion implanted regions 10. The ion implanted regions 10 are highresistance regions, and hence the region in which the FET is to beformed and the region in which the diode is to be formed can beseparated from each other.

[0060] In the ion implantation described above, for example, oxygen ionsare used, and the energy of the oxygen ions is set in accordance withthe thicknesses of the channel layer 3 and the n-type common layer 5. Inthis preferred embodiment, in addition to the separation of the regionin which the FET is to be formed from the region in which the diode isto be formed, the ion implanted regions 10 are formed so as to separatea region in which an FET is to be formed from a region in which a diodeis to be formed, the regions being not shown in the figure and beingadjacent to each other.

[0061] After the ion implantation step is completed as described above,the mask 11 is removed using an organic solvent and/or oxygen plasma.

[0062] Next, as shown in FIG. 4, a source electrode 12 and a drainelectrode 13 for the FET and a cathode 14 for the diode aresimultaneously formed so as to have an ohmic contact with the n-typecommon layer 5. In general, the electrodes 12 to 14 are formedpreferably by a lift-off method.

[0063] More particularly, although not shown in the figure, a mask isfirst formed using a photolithographic technique, and through this mask,a metal is deposited so as to have an ohmic contact, for example, withn-type GaAs forming the n-type common layer 5. Subsequently, by anorganic solvent, the mask is removed together with an unnecessary metalformed thereon. After the removal of the mask described above, metalconductors remaining on the n-type common layer 5 form the sourceelectrode 12, the drain electrode 13, and the cathode 14.

[0064] As a metal deposited in the deposition step described above, inorder to have an ohmic contact, for example, with n-type GaAs formingthe n-type common layer 5, an Au—Ge mixed crystal, In, or other suitablematerial may be used. As one example, a laminate composed of Au—Ge, Ni,and Au may be used. In addition, in order to obtain a superior ohmiccontact, alloying treatment is performed at a temperature ofapproximately 400° C.

[0065] Next, as shown in FIG. 5, a mask 18 is formed by aphotolithographic technique having openings 16 and 17 for exposing agate recess 15 (see FIG. 6) for the FET in the n-type common layer 5 andat least a part of the third etching stopper layer 8.

[0066] Next, as shown in FIG. 6, etching is performed through theopening 16 of the mask 18, and as a result, the gate recess 15 foradjusting the properties of the FET is formed in the n-type common layer5. This etching may be performed by dry etching or wet etching. When wetetching is performed, as an etching solution, for example, a solutioncontaining phosphoric acid, hydrogen peroxide, and water, or a solutioncontaining citric acid, hydrogen peroxide, and water may be used. Thisetching can be easily stopped by the first etching stopper layer 4.

[0067] In addition, through the opening 17 of the mask 18, the etchingis also performed. However, due to the presence of the third etchingstopper layer 8, the p-type layer 7 is prevented from being etched. Inconsideration of the function of the third etching stopper layer 8, thethird etching stopper layer 8 is preferably formed to have a thicknesslarger than the total thickness of the first and the second etchingstopper layers 4 and 6.

[0068] That is, in the etching for forming the gate recess 15 asdescribed above, the second etching stopper layer 6 on the n-type commonlayer 5 is first etched, and at the same time, the third etching stopperlayer 8 on the p-type layer 7 is also etched by the same thickness asthat of the second etching stopper layer 6. Next, when the n-type commonlayer 5 is etched, the third etching stopper layer 8 is notsubstantially etched. Next, when the etching for the n-type common layer5 is completed, this etching was completed. However, at the final stageof this etching, the first etching stopper layer 4 present under then-type common layer 5 is also etched to a certain extent, and inaccordance with the amount etched by this etching described above, thethird etching stopper layer 8 is also etched. Accordingly, in order toallow the third etching stopper layer 8 to remain on the p-type layer 7after the etching is completed as described above, the thickness of thethird etching stopper layer 8 must be larger than the total thickness ofthe first and the second etching stopper layers 4 and 6. Hence, asdescribed above, the thickness of the third etching stopper layer 8 ispreferably larger than the total thickness of the first and the secondetching stopper layers 4 and 6.

[0069] Next, as shown in FIG. 7, through the same mask 18, a gateelectrode 19 used for the FET is formed so as to have a Schottky contactwith the channel layer 3, and at the same time, an anode 20 used for thediode is formed so as to have an ohmic contact with the p-type layer 7.

[0070] The gate electrode 19 and the anode 20 are generally formed by alift-off method. That is, through the mask 18, a metal is deposited, andsubsequently, the mask 18 is removed together with the metal formedthereon by an organic solvent. As a result, the remaining metalconductors form the gate electrode 19 and the anode 20.

[0071] A metal used for forming the gate electrode 19 and the anode 20is a metal which has a Schottky contact, for example, with n-type GaAsforming the channel layer 3 and which has an ohmic contact, for example,with p-type GaAs forming the p-type layer 7, and as the metal describedabove, for example, Ti, Pt, Pd, W, WSi, or Cr may be used. As oneexample, for the gate electrode 19 and the anode 20, a metal laminatecomposed of Ti, Pt, and Au may be used. In addition, in order to realizea superior ohmic contact between the anode 20 and the p-type layer 7,alloying treatment is preferably performed at a temperature ofapproximately 300° C.

[0072] By the steps described above, as shown in FIG. 7, a FET 21 and adiode 22 are formed on the semiconductor substrate 2.

[0073] Next, as shown in FIG. 8, a protective insulating film 23 made,for example, of SiN is formed, and a metal wiring layer 24 forming acircuit is then formed, thereby forming the semiconductor device 1 suchas an MMIC.

[0074] According to the above manufacturing method described above, inaddition to steps of forming a general FET, when only one step offorming the p-type layer 7 for the diode is additionally performed whilethe crystals are grown, the diode functions can be additionallyobtained. As described above, since only one step of forming one layeris additionally performed while the crystals are grown, an increase incost does not substantially occur, and the diode functions can beadvantageously obtained.

[0075] In addition, since the etching for forming the p-type layer forthe diode can be precisely controlled, the variation in properties canbe suppressed as is the case in which the diode is not additionallyprovided.

[0076]FIGS. 9 and 10 are views for illustrating another preferredembodiment of the present invention. FIG. 9 corresponds to FIG. 3, andFIG. 10 corresponds to FIG. 8. The same reference numerals of theelements in FIGS. 3 and 8 designate the same elements in FIGS. 9 and 10,and descriptions thereof are omitted.

[0077] In this preferred embodiment, in order to separate the region inwhich the FET is to be formed from the region in which the diode is tobe formed, etching is performed.

[0078] As in the preferred embodiment described above, after the stepsshown in FIGS. 1 and 2 are performed, as shown in FIG. 9, a mask 31 isformed using a photolithographic technique so as to cover regions inwhich the active layers of the FET and the diode are to be formed.

[0079] Next, through the mask 31, dry etching or wet etching isperformed, thereby removing the channel layer 3 and the n-type commonlayer 5 in regions other than the regions in which the active layers ofthe FET and the diode are to be formed. By this removal using theetching, etching regions 32 are formed, and by the presence of theetching regions 32, the region in which the FET is to be formed isseparated from the region in which the diode is to be formed.

[0080] Subsequently, the mask 31 is removed, and steps substantiallyequivalent to those described with reference to FIGS. 4 to 7 are thenperformed. Next, as shown in FIG. 10, a protective insulating film 23 isformed so as to fill each etching region 32, and the metal wiring layer24 is then formed, thereby forming a semiconductor device 1 a.

[0081] The rest of the structure and the advantages of the preferredembodiment described with reference to FIGS. 9 and 10 are the same asthose of the preferred embodiment described with reference to FIGS. 1 to8.

[0082] In the preferred embodiments described with reference to thefigures, an FET having a single-recess structure is shown. However, evenwhen an FET having a multi-recess structure is formed in which a lowresistance layer is interposed between the n-type common layer 5 and thechannel layer 3, the same advantages as those of the preferredembodiments shown in the figures can also be obtained.

[0083] As described above, according to the method for manufacturing asemiconductor device of preferred embodiments of the present invention,a semiconductor device can be manufactured to include a semiconductorsubstrate, an FET provided thereon having a gate recess and a Schottkyjunction for a gate electrode, and a pn junction diode provided on thesemiconductor substrate, the diode having an n-type layer and a p-typelayer. In the case described above, the diode can be formed withoutsignificantly increasing the number of steps necessary for forming theFET, as described below.

[0084] That is, as the layers formed on the semiconductor substrate byepitaxial growth, the channel layer for the FET, the first etchingstopper layer, the n-type common layer used for the contact layers forthe FET and for the n-type layer for the diode, the second etchingstopper layer, the p-type layer for the diode, and the third etchingstopper layer are mentioned, and among those layers mentioned above, thelayers formed in addition to the layers necessary for forming the FETare only the p-type layer and the third etching stopper layer. Inconsideration of the additional layers, the cost is not substantiallyincreased.

[0085] In addition, after the p-type layer and the third etching stopperlayer in the region in which the FET is to be formed and in the regionin which the cathode of the diode is to be formed are removed by etchingso that the etching is to be stopped by the second etching stopperlayer, the source electrode and the drain electrode for the FET and thecathode for the diode are simultaneously formed so as to have an ohmiccontact with the n-type common layer, and hence a specific step offorming the cathode for the diode is not required.

[0086] Since the mask formed for forming the gate recess is used whenthe gate electrode is formed and, in addition, is also designed to havea function of forming the anode of the diode, the gate electrode and theanode can be simultaneously formed. In the case described above, inetching for forming the gate recess, undesirable etching of the p-typelayer can be advantageously prevented by the presence of the thirdetching stopper layer.

[0087] As described above, compared to the case in which the FET isformed, without substantially increasing the number of manufacturingsteps, the diode can be formed on the same semiconductor substrate.

[0088] In the manufacturing method of preferred embodiments of thepresent invention, when the thickness of the third etching stopper layeris formed to be larger than the total thickness of the first and thesecond etching stopper layers, in the etching step of forming the gaterecess as described above, the p-type layer can be more reliablyprevented from being undesirably etched.

[0089] When the manufacturing method of a semiconductor device,according to preferred embodiments of the present invention, is used, asemiconductor device having the following novel structure can bemanufactured.

[0090] That is, a semiconductor device is formed in which an FET havinga Schottky junction for a gate electrode and a gate recess and a pnjunction diode are formed on the same semiconductor substrate, and inwhich at least one of electrodes of the FET and at least one ofelectrodes of the diode are composed of metal conductors which aresimultaneously formed.

[0091] In more particular, a semiconductor device is formed in which asource electrode and a drain electrode of the FET and a cathode of thediode are composed of metal layers which are simultaneously formed, andin which a gate electrode of the FET and an anode of the diode arecomposed of metal layers which are simultaneously formed.

[0092] In addition, a semiconductor device can be manufactured in whichat least one of active layers of the FET and at least one of activelayers of the diode are composed of layers which are formed from acommon active layer provided on the semiconductor substrate by epitaxialgrowth.

[0093] More particularly, contact layers of the FET and an n-type layerof the diode are preferably composed of layers which are formed from acommon n-type layer, that is, the n-type common layer, and in even moreparticular, the structure can be obtained in which the contact layersare provided on the channel layer on the semiconductor substrate forforming the FET and in which the p-type layer of the diode is providedon the n-type layer thereof.

[0094] The present invention is not limited to each of theabove-described preferred embodiments, and various modifications arepossible within the range described in the claims. An embodimentobtained by appropriately combining technical features disclosed in eachof the different preferred embodiments is included in the technicalscope of the present invention.

What is claimed is:
 1. A semiconductor device comprising: asemiconductor substrate; a field effect transistor provided on thesemiconductor substrate and having electrodes, the transistor having agate recess and a Schottky junction for a gate electrode; and a pnjunction diode provided on the semiconductor substrate and havingelectrodes, the pn junction diode having an n-type layer and a p-typelayer; wherein at least one of the electrodes of the field effecttransistor and at least one of the electrodes of the pn junction diodeare composed of metal conductors which are simultaneously formed.
 2. Thesemiconductor device according to claim 1, wherein a source electrodeand a drain electrode of the field effect transistor and a cathode ofthe pn junction diode are composed of metal conductors which aresimultaneously formed.
 3. The semiconductor device according to claim 1,wherein the gate electrode of the field effect transistor and an anodeof the pn junction diode are composed of metal conductors which aresimultaneously formed.
 4. The semiconductor device according to claim 1,wherein at least one of active layers of the field effect transistor andat least one of active layers of the diode are composed of layers whichare obtained from a common active layer which is epitaxially grown. 5.The semiconductor device according to claim 4, wherein contact layers ofthe field effect transistor and of the n-type layer of the pn junctiondiode are composed of layers which are obtained from a common n-typelayer provided on the semiconductor substrate which is epitaxiallygrown.
 6. The semiconductor device according to claim 5, wherein thecontact layers are provided on a channel layer on the semiconductorsubstrate of the field effect transistor, and the p-type layer of the pnjunction diode is provided on the n-type layer thereof.
 7. Thesemiconductor device according to claim 4, wherein the active layer ofthe field effect transistor is separated from the active layer of thediode.
 8. A semiconductor device comprising: a semiconductor substrate;a field effect transistor provided on the semiconductor substrate andhaving electrodes, the transistor having a gate recess and a Schottkyjunction for a gate electrode; and a pn junction diode provided on thesemiconductor substrate and having electrodes, the pn junction diodehaving an n-type layer and a p-type layer; wherein a source electrodeand a drain electrode of the field effect transistor and a cathode ofthe pn junction diode are composed of metal conductors which aresimultaneously formed; and the gate electrode of the field effecttransistor and an anode of the pn junction diode are composed of metalconductors which are simultaneously formed.
 9. The semiconductor deviceaccording to claim 8, wherein at least one of the electrodes of thefield effect transistor and at least one of the electrodes of the pnjunction diode are composed of metal conductors which are simultaneouslyformed.
 10. The semiconductor device according to claim 8, wherein atleast one of active layers of the field effect transistor and at leastone of active layers of the diode are composed of layers which areobtained from a common active layer which is epitaxially grown.
 11. Thesemiconductor device according to claim 10, wherein contact layers ofthe field effect transistor and of the n-type layer of the pn junctiondiode are composed of layers which are obtained from a common n-typelayer provided on the semiconductor substrate which is epitaxiallygrown.
 12. The semiconductor device according to claim 11, wherein thecontact layers are provided on a channel layer on the semiconductorsubstrate of the field effect transistor, and the p-type layer of the pnjunction diode is provided on the n-type layer thereof.
 13. Thesemiconductor device according to claim 10, wherein the active layer ofthe field effect transistor is separated from the active layer of thediode.
 14. A method for manufacturing a semiconductor device including asemiconductor substrate, a field effect transistor provided on thesemiconductor substrate and having a gate recess and a Schottky junctionfor a gate electrode, and a pn junction diode provided on thesemiconductor substrate, the method comprising: a step of preparing thesemiconductor substrate; a step of forming a channel layer for the fieldeffect transistor, a first etching stopper layer, an n-type common layerused for contact layers for the field effect transistor and for ann-type layer for the diode, a second etching stopper layer, a p-typelayer for the diode, and a third etching stopper layer on thesemiconductor substrate in that order by epitaxial growth; an etchingstep of etching away the p-type layer and the third etching stopperlayer in regions in which the field effect transistor and a cathode ofthe diode are to be formed so that the etching is to be stopped by thesecond etching stopper layer; a step of simultaneously forming a sourceelectrode and a drain electrode for the field effect transistor and thecathode for the diode so as to have an ohmic contact with the n-typecommon layer; a step of forming a mask having openings which expose aregion of the n-type common layer in which the gate recess for the fieldeffect transistor is to be formed and at least a portion of the thirdetching stopper layer; a step of performing etching through the mask forforming the gate recess in the n-type common layer while the thirdetching stopper layer prevents the p-type layer from being etched, inwhich the etching is stopped by the first etching stopper layer; a stepof simultaneously forming the gate electrode for the field effecttransistor which has a Schottky contact with the channel layer and ananode for the diode which has an ohmic contact with the p-type layerthrough the mask; and a step of removing the mask.
 15. The method formanufacturing a semiconductor device, according to claim 14, furthercomprising, after the etching step: performing etching or ionimplantation for the channel layer and the n-type common layer in orderto separate a region in which the field effect transistor is to beformed from a region in which the diode is to be formed.
 16. The methodfor manufacturing a semiconductor device, according to claim 14, whereinthe third etching stopper layer is formed to have a thickness that islarger than a total thickness of the first and the second etchingstopper layers.